DGRH-EDA — Formal Verification Engine

GEOMETRIC FORMAL VERIFICATION

// proves hardware properties using algebraic structure — not exhaustive search

STANDALONE · NO SAT SOLVER ZERO TRAINING DATA VERILOG READY COMPETES WITH SYNOPSYS · CADENCE · Z3

Circuit Configuration

// select circuit type

// bit width

8 bit

48162432

// verilog preview

module adder_8bit( input [7:0] a, b, output [7:0] sum ); assign sum = a + b; endmodule

// DGRH ADMISSIBILITY

Adm(v,n) = { dr(v) ∈ {3,6,9} } ρ(n) = |Adm(n)| / 2ⁿ = 1/3 Reduction = 1 − ρ² = 88.89% Safety ← f(a,b) = g(a,b) & mask Complexity = O(1) ←→ Z3: O(2²ⁿ)

Performance vs Z3 4.16.0

—x

SPEEDUP OVER Z3

— ms total

SAFETY

—

OVERFLOW

—

CLOSURE

—

DEADLOCK

—

LIVELOCK

—

SAFETY

O(1)

Awaiting verification...

—

OVERFLOW

O(n)

Awaiting verification...

—

CLOSURE

O(1)

Awaiting verification...

—

DEADLOCK

O(1)

Awaiting verification...

—

LIVELOCK

O(1)

Awaiting verification...

—

dgrh-verifier — output

$ dgrh-verify --engine=v2.2 --mode=symbolic ✓ DGRH Engine v2.2 loaded ✓ Z3 baseline: 4.16.0 ✓ Ready — select circuit and press VERIFY

Benchmark History — All Circuits × All Bit Widths

CIRCUIT	BITS	DGRH (ms)	Z3 (ms)	SPEEDUP	SOUND	ADVANTAGE
— run verification to populate —